`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

localparam S0=2'b00;
localparam S1=2'b01;
localparam S2=2'b10;
localparam S3=2'b11;

reg [1:0]state;
reg [1:0]next_state;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		state<=S0;
	else
		state<=next_state;
end
reg Y_r;
always@(*)begin
	case(state)
		S0:begin
			next_state=(C)?S1:S0;
			Y_r=1'b0;
		end
		S1:begin
			next_state=(C)?S1:S3;
			Y_r=1'b0;
		end
		S2:begin
			next_state=(C)?S2:S0;
			Y_r=C;
		end
		S3:begin
			next_state=(C)?S2:S3;
			Y_r=1'b1;
		end
	endcase
end
assign Y=Y_r;
endmodule